Recent innovations in three-dimensional (3D) chip, die and wafer integration (hereinafter, collectively, stacked structures) have enabled a greater miniaturization of devices as well as technological advancements in increased speed and density, with reduced power consumption and cost. Wafer packaging technology on a wafer-level allows for vertical stacking of two or more wafers and to provide electrical connection and hermetical sealing between the wafers.
Various wafer bonding techniques have been developed and employed to join two or more wafers of the same or different types. However, fabrication of micro-electromechanical systems (MEMS) device involves making released structures that move mechanically, thereby resulting in, among other issues, stiction between surfaces and thermal stress induced instability in the final device.
From the foregoing discussion, it is desirable to provide a wafer level packaging for MEMS device that reduces stiction, improves thermal stability and hermetic or vacuum sealing in the final device.